Optional firmware package for the onboard FPGA
ADX corrects TI-ADC offset, gain and phase errors so that unwanted image spurs does not limit achievable SFDR.
FW2DDC contains two digital downconverters (DDCs) consisting of quadrature mixers and decimation filters that help reduce the data rate, improve the signal-to-noise (SNR) ratio for the band of interest, and translate the RF frequency to an intermediate frequency (IF) for baseband processing.
The subsequent finite impulse response (FIR) filters can be used either for further noise reduction, for channel equalization, or for correcting in-phase and quadrature (IQ) imbalance.
Firmware updates can be done by the user via the ADQUpdater tool that is included in the SDK

Description

FW2DDC equips ADQ7WB and ADQ7DC with real-time functions commonly used in radio frequency (RF) receivers. It also contains the proprietary ADX technology which corrects mismatch errors in time-interleaved analog-to-digital converters (TI-ADCs) and thereby ensure industry-leading spurious-free dynamic range (SFDR). The digital signal processing also helps reduce the data rate to a manageable level in order to simplify data post-processing and storage.

Key Specifications

Built-in ADX time-interleaving correction

DDC

DDC instances	2
NCO frequency resolution	1.1642 Hz
NCO spur level	-95 dBFS
Decimation factor	2 to 2^34

FIR filter / Equalizer

Filter instances	4
Filter length	5 taps
Coefficient length	14 bits
Data input length	Up to 25 bits

Applications