Time-of-flight mass spectrometry (TOFMS) is an analytical technique that separates ions based on their mass-to-charge ratio (m/z) by measuring the time required for ions to travel through a field-free flight tube. After acceleration by an electric field, ions are separated according to their velocities — lighter ions reach the detector before heavier ones.
The digitizer plays a critical role in TOFMS systems by capturing the transient electrical pulses generated when ions strike the detector. These pulses are typically very brief (nanoseconds to microseconds) and must be sampled at high rates with sufficient resolution to accurately quantify ion abundance across a wide dynamic range.
Modern TOFMS applications demand digitizers capable of not only high-speed acquisition but also advanced signal processing, baseline stabilization, and data reduction to handle the enormous data volumes generated during high-throughput analysis. The basic principle is illustrated in figure 1.
Programmable DC offset allows users to maximize the effective input range while preventing signal saturation. This feature is critical in TOFMS where baseline drift can cause signals to shift outside the optimal digitizer range.
Figure 2. DC offset is a crucial feature needed to fully utilize the digitizers input range while avoiding overflow/saturation.
Corrects slow baseline drift caused by temperature variations, detector aging, or environmental factors. The DBS continuously monitors and compensates for DC shifts, ensuring stable measurements throughout extended acquisition sessions.
Figure 3. Uncorrected baseline fluctuation/drift may result in missed pulses (top). With DBS this is corrected (bottom).
On-board FPGA processing enables real-time peak detection, integration, and data compression. This significantly reduces the volume of data transferred to the host system while preserving critical signal fidelity and measurement accuracy.
Figure 4. The onboard FPGA is crucial for reducing the data rate so that it matches the link capacity without loss of signal information.
Averaging involves accumulating a large number of waveforms (records) and subsequently scaling by the total number of accumulated waveforms. The accumulation functionality is available through the FWATD firmware option. This process effectively suppresses random noise and enhances systematic (periodic) signals.
However, when a large number of records are accumulated, systematic noise may become apparent. Refer to the figure below, where the left-hand red curve illustrates accumulated systematic noise at 6 µV. This type of noise is amplified when the trigger is correlated with the noise source.
To mitigate this, decorrelating the trigger frequency from the noise source can suppress the systematic noise. The green and blue curves in the figure demonstrate the resulting noise suppression.
Decorrelation can be achieved through various methods, though care must be taken to avoid introducing jitter. In the right-hand figure, the green pulse exhibits jitter and is broadened as a result. In contrast, the red and blue pulses remain sharp, indicating the absence of jitter.
The ADQ35 and ADQ35-PDRX digitizers incorporate a fractional-N PLL-based trigger source, which enables both systematic noise suppression and low jitter performance, as demonstrated by the blue curves in both plots.
For further details, refer to the application note 25-3162 ADQ35-PDRX FWATD trigger
The application note outlines a method for achieving noise suppression during waveform accumulation. It is recommended for use with the ADQ35 and ADQ35-PDRX devices when accumulating a large number of waveforms.
The method relies on a Fractional-N PLL, which requires the ADQ35 to act as the timing master within the system. This may necessitate some system-level redesign. For scenarios where only the pulse source needs to be triggered, figure 7 in the application note provides a viable solution. If more precisely controlled signals are required, this approach remains applicable but with minor modifications.
In this configuration, the Fractional-N PLL triggers the pulse source and simultaneously serves as a clock reference for an FPGA or microprocessor, the generation of states and control signals as illustrated below.
If the trigger rate is too low to support PLL operation, a higher frequency can be used, with a gating mechanism applied to set the desired trigger rate for the pulse source.
This setup ensures synchronization across all system components, enhancing timing precision and signal integrity.
배송안내
배송 지역 | 대한민국 전지역
배송비 | 2,500원 (50,000원 이상 결제시 무료배송)
배송기간 | 주말 공휴일 제외 2~5일
- 모든 배송은 택배사 사정으로 지연될 수 있습니다.
교환 및 반품 안내
- 고객 변심으로 인한 교환/반품은 상품 수령 후 14일 이내 가능합니다.
- 고객 귀책 사유로 인한 반품의 경우 왕복 택배비는 고객 부담입니다.
- 반품접수 기한이 지난 경우, 제품 및 패키지 훼손, 사용 흔적이 있는 제품은 교환/반품이 불가합니다.
Time-of-flight mass spectrometry (TOFMS) is an analytical technique that separates ions based on their mass-to-charge ratio (m/z) by measuring the time required for ions to travel through a field-free flight tube. After acceleration by an electric field, ions are separated according to their velocities — lighter ions reach the detector before heavier ones.
The digitizer plays a critical role in TOFMS systems by capturing the transient electrical pulses generated when ions strike the detector. These pulses are typically very brief (nanoseconds to microseconds) and must be sampled at high rates with sufficient resolution to accurately quantify ion abundance across a wide dynamic range.
Modern TOFMS applications demand digitizers capable of not only high-speed acquisition but also advanced signal processing, baseline stabilization, and data reduction to handle the enormous data volumes generated during high-throughput analysis. The basic principle is illustrated in figure 1.
Programmable DC offset allows users to maximize the effective input range while preventing signal saturation. This feature is critical in TOFMS where baseline drift can cause signals to shift outside the optimal digitizer range.
Figure 2. DC offset is a crucial feature needed to fully utilize the digitizers input range while avoiding overflow/saturation.
Corrects slow baseline drift caused by temperature variations, detector aging, or environmental factors. The DBS continuously monitors and compensates for DC shifts, ensuring stable measurements throughout extended acquisition sessions.
Figure 3. Uncorrected baseline fluctuation/drift may result in missed pulses (top). With DBS this is corrected (bottom).
On-board FPGA processing enables real-time peak detection, integration, and data compression. This significantly reduces the volume of data transferred to the host system while preserving critical signal fidelity and measurement accuracy.
Figure 4. The onboard FPGA is crucial for reducing the data rate so that it matches the link capacity without loss of signal information.
Averaging involves accumulating a large number of waveforms (records) and subsequently scaling by the total number of accumulated waveforms. The accumulation functionality is available through the FWATD firmware option. This process effectively suppresses random noise and enhances systematic (periodic) signals.
However, when a large number of records are accumulated, systematic noise may become apparent. Refer to the figure below, where the left-hand red curve illustrates accumulated systematic noise at 6 µV. This type of noise is amplified when the trigger is correlated with the noise source.
To mitigate this, decorrelating the trigger frequency from the noise source can suppress the systematic noise. The green and blue curves in the figure demonstrate the resulting noise suppression.
Decorrelation can be achieved through various methods, though care must be taken to avoid introducing jitter. In the right-hand figure, the green pulse exhibits jitter and is broadened as a result. In contrast, the red and blue pulses remain sharp, indicating the absence of jitter.
The ADQ35 and ADQ35-PDRX digitizers incorporate a fractional-N PLL-based trigger source, which enables both systematic noise suppression and low jitter performance, as demonstrated by the blue curves in both plots.
For further details, refer to the application note 25-3162 ADQ35-PDRX FWATD trigger
The application note outlines a method for achieving noise suppression during waveform accumulation. It is recommended for use with the ADQ35 and ADQ35-PDRX devices when accumulating a large number of waveforms.
The method relies on a Fractional-N PLL, which requires the ADQ35 to act as the timing master within the system. This may necessitate some system-level redesign. For scenarios where only the pulse source needs to be triggered, figure 7 in the application note provides a viable solution. If more precisely controlled signals are required, this approach remains applicable but with minor modifications.
In this configuration, the Fractional-N PLL triggers the pulse source and simultaneously serves as a clock reference for an FPGA or microprocessor, the generation of states and control signals as illustrated below.
If the trigger rate is too low to support PLL operation, a higher frequency can be used, with a gating mechanism applied to set the desired trigger rate for the pulse source.
This setup ensures synchronization across all system components, enhancing timing precision and signal integrity.
배송안내
배송 지역 | 대한민국 전지역
배송비 | 2,500원 (50,000원 이상 결제시 무료배송)
배송기간 | 주말 공휴일 제외 2~5일
- 모든 배송은 택배사 사정으로 지연될 수 있습니다.
교환 및 반품 안내
- 고객 변심으로 인한 교환/반품은 상품 수령 후 14일 이내 가능합니다.
- 고객 귀책 사유로 인한 반품의 경우 왕복 택배비는 고객 부담입니다.
- 반품접수 기한이 지난 경우, 제품 및 패키지 훼손, 사용 흔적이 있는 제품은 교환/반품이 불가합니다.
